As semiconductor manufacturers continually try to reduce the feature size of semiconductor devices, line-to-line capacitance becomes a problem. When metal lines of a semiconductor device are patterned closer and closer together, the dielectric constant (k) of any interlayer dielectric used needs to be reduced in order to prevent the capacitance between those lines from increasing. Conventional interlayer dielectrics (ILDs) in the form of chemical vapor deposition (CVD) oxide, such as that deposited from tetraethylorthosilicate (TEOS), have k values of approximately 3.9 to 4.1. For future generation devices, for instance devices with minimum feature sizes at or below 0.25 micron, it is believed that these dielectric films will produce unacceptable line-to-line capacitance and that lower k dielectric films will be needed.
One attempt to reduce the dielectric constant of an interlayer oxide is to fluorinate the oxide during deposition. However, the resulting reduction in the dielectric constant is of insufficient magnitude to result in a dramatic difference in line-to-line capacitance. For example, fluorinated oxides have a k value of between 3.4 and 3.6. Other materials have been able achieve a k value of about 3.0, for example silsesquioxanes. Polyimides are another material being evaluated for low k applications. Polyimides typically have k values between 3.2 and 3.3 Some polymers have been introduced which result in k values of even less than 3, for example Cyclotene 5021 by Lucent Technologies and Parylene VIP AF-4 by Specialty Coating Systems.
Despite the fact that low k polymers exist, few have achieved success in use in semiconductor manufacturing for a variety of reasons. One problem is that photoresist cannot be deposited directly on the polymer to pattern vias in the polymer. Photoresist can be either miscible or partially miscible with the underlying polymer. The former causes the photoresist to solubilize the polymer ILD. The latter would create an interfacial layer between the photoresist and interlayer dielectric which could adversely effect patterning or removal of the photoresist layer. A proposed solution to this problem is to deposit an oxide or spin-on-glass (SOG) layer as a hard mask on top of the polymeric interlayer dielectric prior to the deposition of photoresist. However, the problem with using an oxide, such as by chemical vapor deposition (CVD), is that it is deposited at a high temperature which can be harmful to the underlying polymer. Exposing the polymer interlayer dielectric to high temperatures during oxide deposition can adversely affect its dielectric constant (by raising it) and cause the polymer layer to flow. While SOGs can be deposited at low temperatures, the use of SOGs impose particulate problems in manufacturing and either must be removed or capped with a subsequent layer, thus introducing additional processing steps.
Accordingly, there is a need in the art of semiconductor manufacturing to be able to deposit a low k dielectric film in a semiconductor device to reduce line-to-line capacitance, while at the same time overcoming the miscibility and high temperature incompatibility problems associated with prior art low k dielectric materials.